立木馨大 - Semicon Lab.

超低損失SiC MOSFET実現に向けた界面準位の
低減および設計指針の提示

K. Tachiki, T. Ono, T. Kobayashi, H. Tanaka, and T. Kimoto,
“Estimation of threshold voltage in SiC short channel MOSFETs”,
IEEE Trans. Electron Devices, 65, 3077 (2018).
K. Tachiki, M. Kaneko, T. Kobayashi, and T. Kimoto,
“Formation of high-quality SiC(0001)/SiO₂ structures by excluding oxidation process with H₂ etching before SiO₂ deposition and high-temperature N₂ annealing”,
Appl. Phys. Express, 13, 121002 (2020).
K. Tachiki and T. Kimoto,
“Improvement of Both n- and p-Channel Mobilities in 4H-SiC MOSFETs by High-Temperature N₂ Annealing”
IEEE Trans. Electron Devices, 68, 638 (2021).
K. Tachiki, M. Kaneko, and T. Kimoto
“Mobility improvement of 4H-SiC (0001) MOSFETs by a three-step process of H₂ etching, SiO₂ deposition, and interface nitridation”
Appl. Phys. Express, 14, 031001 (2021).
K. Tachiki, T. Ono, T. Kobayashi, and T. Kimoto,
“Short-Channel Effects in SiC MOSFETs Based On analyses of Saturation Drain Current”,
IEEE Trans. Electron Devices, 68, 1382 (2021).

K. Tachiki and T. Kimoto, “Impact of high-temperature nitrogen annealing on interface properties of p-type 4H-SiC/SiO₂”, The 9th Asia-Pacific Workshop on Widegap Semiconductors, ThP-HC-13, Okinawa, Japan, 9/ 2019
K. Tachiki and T. Kimoto, “Reduction of interface states in 4H-SiC/SiO₂ near both conduction and valence band edges by high-temperature nitrogen annealing”, International Conference on Silicon Carbide & Related Materials 2019, Mo-2A-05, Kyoto, Japan, 9-10/2019
K. Tachiki, T. Ono, T. Kobayashi, and T. Kimoto, “Estimation of threshold voltage in SiC short-channel MOSFETs”, International Conference on Silicon Carbide & Related Materials 2017, TU.04a.04, Birmingham, UK, 9/2018.
K. Tachiki , T. Ono, T. Kobayashi and T. Kimoto, “Experimental study on short channel effects in 4H-SiC MOSFETs”, International Conference on Silicon Carbide & Related Materials 2017, TU.DP.16, Washington DC, USA, 9/2017 Late News.